Within electronic circuitry, a direct current to direct current (DC-DC) voltage-mode boost converter circuit can be utilized as a voltage supply for other circuitry. It is appreciated that a DC-DC voltage-mode boost converter circuit typically receives an input voltage at one value and generates an output voltage having a value greater than or equal to the input voltage. It is desirable that the DC-DC voltage-mode boost converter circuit provides a stable output voltage so that the circuitry connected to it can operate properly. However, there are disadvantages associated with conventional DC-DC voltage-mode boost converter circuits.
For example, when the load current of the DC-DC voltage-mode boost converter circuit changes quickly, it can cause the output voltage of the DC-DC voltage-mode boost converter to become unstable or transient for a period of time. Unfortunately, the time it takes the output voltage of the DC-DC voltage-mode boost converter to return to its stable value can be slow (known as its transient response). Therefore, the slow transient response can cause circuitry connected to the DC-DC voltage-mode boost converter to not operate properly. Additionally, the DC-DC voltage-mode boost converter is a negative feedback loop system, wherein there is a 180-degree phase shift at DC conditions. At higher frequency, reactive components and time delays can adversely cause extra time shifts within the DC-DC voltage-mode boost converter.
One conventional solution for trying to solve these disadvantages is to implement a compensation circuit, such as compensation circuit 1200 of FIG. 12, in the loop of the DC-DC voltage-mode boost converter, which guarantees enough phase margin by limiting the gain and crossover frequency of the loop. Unfortunately, the compensation circuit 1200 usually adversely limits the loop speed of the transient response. The compensation circuit 1200 is usually composed of fixed-value resistors 1206 and 1208 and fixed-value capacitors 1202 and 1204, which values are usually determined based upon worst-case input, output, and load conditions. As such, in normal operating conditions, the phase margin can be much more than needed, thereby resulting in the speed of the loop load transient or line transient being slow.
Therefore, it would be desirable to address one or more of the above disadvantages.